FPGA PRET Accelerators of Deep Learning Classifiers for Autonomous Vehicles

About This Project

At a glance

This project focuses on predictable, repeatable and transparent (PRET) computation infrastructure for efficient implementation of safety critical cyber-physical systems (CPS), such as control systems in autonomous vehicles. Deep Learning (DL) is a promising approach to sensing in this space. However, it is unclear how DL-based sensor implementations would influence the control structures, due to standard implementations that largely ignore timing and energy constraints present in embedded settings. This project will investigate how to leverage previously developed PRET technology and develop timing predictable, energy optimized classifier implementations.

In recent work, the team focused on PRET challenges in numerical computation for high-performance control system design. A highly parameterized processor template based on Very Long Instruction Word (VLIW) architecture was developed (shown below), along with a set of highly transparent programming tools. The architecture is characterized by complete predictability and repeatability of computation timing, to facilitate design and verification of control systems. The template-based generator approach allows researchers to quickly and easily specialize processor instance according to the needs of the computation to be accelerated. The scalar type, number of parallel units, and memories can be changed at any point during design. In combination with transparent programming tools, this allows the team to quickly discover latency versus energy efficiency tradeoffs for computations and quickly configure processors instances.

For this project, the team aims to create Deep Learning Classifier implementations on embedded hardware (FPGAs) interfacing their generator tools directly to Caffe. 

 
Principal InvestigatorsResearchersThemes

Vladimir Stojanovic

Ranko SredojevicDeep Learning

 

BAIR/CPAR/BDD Internal Weekly Seminar

Event Location: 
250 Sutardja Dai Hall

The Berkeley Artificial Intelligence Research Lab co-hosts a weekly internal seminar series with the CITRIS People and Robots Initiative and the Berkeley Deep Drive Consortium. The seminars are every Friday afternoon in room 250 Sutardja Dai Hall from 3:10-4:10 PM, and are open to BAIR/BDD faculty, students, and sponsors. Seminars will be webcast live and recorded talks will be available online following the seminar. 

Schedule:

http://citris-uc.org/bair-seminar-series/